HD64F2149 Datasheet, PDF (377/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,
Timer Control Register.
12.2.7 System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E IOSE INTM1 INTM0 XRST NMIEG HIE RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write ^{R/W R/W}
R
R/W
R
R/W R/W R/W
Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections
3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data
registers and control registers, and timer connection control registers.
Bit 1
HIE
0
1
Description
CPU access to 8-bit timer (channel X and Y) data registers and control (Initial value)
registers, and timer connection control registers, is enabled
CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is disabled
12.2.8 Timer Connection Register S (TCONRS)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TMRX/Y ISGENE HOMOD1HOMOD0 VOMOD1VOMOD0 CLMOD1 CLMOD0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY
registers and timer connection operation.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.
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