HD64F2149 Datasheet, PDF (636/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR1 Bit 0—HIRQ6 Interrupt Enable 2 (IRQ6E2): Enables or disables a HIRQ6 interrupt
request when OBF2 is set by an ODR2 write.
Bit 0
IRQ6E2
0
1
Description
HIRQ6 interrupt request by OBF2 and IRQ6E2 is disabled
[Clearing conditions]
• Writing 0 to IRQ6E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is enabled
[When IEDIR = 1]
HIRQ6 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ6E2 = 0
(Initial value)
SIRQCR0 Bit 1—HIRQ12 Interrupt Enable 1 (IRQ12E1): Enables or disables a HIRQ12
interrupt request when OBF1 is set by an ODR1 write.
Bit 1
IRQ12E1
0
1
Description
HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled
[Clearing conditions]
• Writing 0 to IRQ12E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
HIRQ12 interrupt request by setting OBF1 to 1 is enabled
[Setting condition]
• Writing 1 after reading IRQ12E1 = 0
(Initial value)
602