HD64F2149 Datasheet, PDF (896/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

LADR3H—LPC Channel 3 Address Register H
LADR3L—LPC Channel 3 Address Register L
H'FE34
H'FE35
HIF (LPC)
HIF (LPC)
LADR3H
LADR3L
Bit
Initial value
Read/Write
7 65 43 21 07 65 43 21 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — Bit 1 TWRE
0 00 00 00 00 00 00 00 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓
↓
IDR3, ODR3, _{Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1/0 Bit 1 0}
STR3 address
↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓
TWR0–TWR15 _{Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 1/0 1/0 1/0 1/0}
address
Channel 3 address bits 15 to 3 and 1
Register selection according to the bits ignored in address match determination is as shown in
the following table.
Bit 4
I/O address
Bit 3 Bit 2 Bit 1
Bit 0
Transfer
cycle
Host register selection
Bit 4 Bit 3
0
Bit 1
0 I/O write IDR3 write, C/D3 ← 0
Bit 4 Bit 3
1
Bit 1
0 I/O write IDR3 write, C/D3 ← 1
Bit 4 Bit 3
0
Bit 1
0 I/O read ODR3 read
Bit 4 Bit 3
1
Bit 1
0 I/O read STR3 read
Bit 4
0
0
0
0 I/O write TWR0MW write
Bit 4
0
1
0
0
•••
1
1
1 I/O write TWR1 write to TWR15 write
1
Bit 4
0
0
0
0 I/O read TWR0SW read
Bit 4
0
1
0
0
•••
1
1
1 I/O read TWR1 read to TWR15 read
1
Two-way register enable
LADR3L
Bit 0
Description
TWRE
0
TWR operation is disabled
TWR-related I/O address match determination is halted
1
TWR operation is enabled
862