HD64F2149 Datasheet, PDF (630/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• SIRQCR1
Bit
7
6
5
4
3
2
1
0
IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2
Initial value
0
0
0
0
0
0
0
0
Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Host Read/Write
—
—
—
—
—
—
—
—
The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that
specify SERIRQ interrupt sources.
The SIRQCR registers are initialized to H'00 by a reset and in hardware standby mode.
SIRQCR0 Bit 7—Quiet/Continuous Mode Flag (Q/C): Indicates the mode specified by the host
at the end of an SERIRQ transfer cycle (stop frame).
Bit 7
Q/C
0
1
Description
Continuous mode
[Clearing conditions]
• LPC hardware reset, LPC software reset
• Specification by SERIRQ transfer cycle stop frame
Quiet mode
[Setting condition]
• Specification by SERIRQ transfer cycle stop frame
(Initial value)
SIRQCR0 Bit 6—Reserved: This is a readable/writable reserved bit.
SIRQCR0 Bit 5—Interrupt Enable Direct Mode (IEDIR): Specifies whether LPC channel 2
and channel 3 SERIRQ interrupt source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation is
conditional upon OBF, or is controlled only by the host interrupt enable bit.
Bit 5
IEDIR
0
1
Description
Host interrupt is requested when host interrupt enable bit and corresponding
OBF are both set to 1
(Initial value)
Host interrupt is requested when host interrupt enable bit is set to 1
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