HD64F2149 Datasheet, PDF (217/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
DTC activation
request
DTC
request
Address
Vector read
Data transfer
Read Write
Data transfer
Read Write
Transfer
information
read
Transfer Transfer
information information
write
read
Transfer
information
write
Figure 7.12 DTC Operation Timing (Chain Transfer)
7.3.10 Number of DTC Execution States
Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of
states required for each execution phase.
Table 7.8 DTC Execution Phases
Mode
Normal
Repeat
Block transfer
Vector Read
I
1
1
1
Register Information
Internal
Read/Write
Data Read Data Write Operation
J
K
L
M
6
1
1
3
6
1
1
3
6
N
N
3
N: Block size (initial setting of CRAH and CRAL)
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