HD64F2149 Datasheet, PDF (740/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 23.4 and figure 23.6 show the input conditions for the external clock.
Table 23.4 External Clock Input Conditions
Item
External clock input low pulse width
External clock input high pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
V_CC = 2.7 to 3.6 V
Symbol Min Max
Unit
t _EXL
40
—
ns
t _EXH
40
—
ns
t _EXr
—
10
ns
t _EXf
—
10
ns
t _CL
0.4
0.6
t _cyc
80
—
ns
t _CH
0.4
0.6
t _cyc
80
—
ns
Test Conditions
Figure 23.6
ø ≥ 5 MHz Figure 25.4
ø < 5 MHz
ø ≥ 5 MHz
ø < 5 MHz
EXTAL
t_EXH
t_EXL
V_CC × 0.5
t_EXr
t_EXf
Figure 23.6 External Clock Input Timing
Table 23.5 shows the external clock output settling delay time, and figure 23.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock
signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the
external clock output settling delay time (t_DEXT). As the clock signal output is not fixed during the
t_DEXT period, the reset signal should be driven low to maintain the reset state.
706