HD64F2149 Datasheet, PDF (320/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with
14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode, and by the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
0
1
Description
DADRA and DADRB can be accessed
DACR and DACNT can be accessed
(Initial value)
10.2.2 D/A Data Registers A and B (DADRA and DADRB)
DADRH
DADRL
Bit (CPU)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit (Data)
13 12 11 10 9 8 7 6 5 4 3 2 1 0 — —
DADRA
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS —
Initial value ^{1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1}
Read/Write ^{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —}
DADRB
Initial value
Read/Write
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
1 1 111 11 11 1 111 111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM (D/A) channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
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