HD64F2149 Datasheet, PDF (892/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

IDR3—Input Data Register 3
IDR1—Input Data Register 1
IDR2—Input Data Register 2
H'FE30
H'FE38
H'FE3C
HIF (LPC)
HIF (LPC)
HIF (LPC)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R
W
6
Bit 6
—
R
W
5
Bit 5
—
R
W
4
Bit 4
—
R
W
3
Bit 3
—
R
W
2
Bit 2
—
R
W
1
Bit 1
—
R
W
0
Bit 0
—
R
W
Written by host using I/O address in table below*
I/O address
Transfer
Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 ^cycle
Host register
selection
0000 0000 0110 0 0 0 0 I/O write IDR1 write, C/D1 ← 0
0000 0000 0110 0 1 0 0 I/O write IDR1 write, C/D1 ← 1
0000 0000 0110 0 0 1 0 I/O write IDR2 write, C/D2 ← 0
0000 0000 0110 0 1 1 0 I/O write IDR2 write, C/D2 ← 1
Note: * For information on IDR3 selection, see LPC Channel 3 Address
Register (LADR3).
858