HD64F2149 Datasheet, PDF (594/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in
hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1)
HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)
These bits enable or disable the IBF1, IBF2, IBF3, and IBF4 interrupts to the internal CPU.
HICR2
Bit 2
IBFIE4
—
—
—
—
—
—
0
1
HICR2
Bit 1
IBFIE3
—
—
—
—
0
1
—
—
HICR
Bit 2
IBFIE2
—
—
0
1
—
—
—
—
HICR
Bit 1
IBFIE1
0
1
—
—
—
—
—
—
Description
Input data register (IDR1) reception completed interrupt
request disabled
(Initial value)
Input data register (IDR1) reception completed interrupt
request enabled
Input data register (IDR2) reception completed interrupt
request disabled
(Initial value)
Input data register (IDR2) reception completed interrupt
request enabled
Input data register (IDR3) reception completed interrupt
request disabled
(Initial value)
Input data register (IDR3) reception completed interrupt
request enabled
Input data register (IDR4) reception completed interrupt
request disabled
(Initial value)
Input data register (IDR4) reception completed interrupt
request enabled
HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate
function. When the fast A20 gate is disabled, the normal A20 gate can be implemented byte
firmware operation of the P81 output.
When the host interface (HIF:XBS) fast A20 gate function is enabled, the DDR bit for P81 must
be set to 1. Therefore, the state of the P81/GA20 pin cannot be monitored by reading the DR bit
for P81.
A fast A20 gate function is also provided in the HIF:LPC. The state of the P81/GA20 pin can be
monitored by reading the HIF:LPC’s GA20 bit.
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