HD64F2149 Datasheet, PDF (547/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
7
8
9
Bit 1 Bit 0
Data 1
[4]
A
RDRF
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[4]
A
IRIC
ICDRS
Interrupt
request
generation
Data 1
Interrupt
request
generation
Data 2
ICDRR
Data 1
Data 2
User processing
[5] ICDR read [5] IRIC clearance
Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)
16.3.5 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
[2] When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At
the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU. .If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set
to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is
written.
[3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.
The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR
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