HD64F2149 Datasheet, PDF (590/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18A.1.4 Register Configuration
Table 18A.2 lists the HIF:XBS registers. HIF:XBS registers HICR, IDR1, IDR2, ODR1, ODR2,
STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 18A.2 Register Configuration
Name
Abbrevia-
R/W
Initial Slave
Host Address*⁴
tion
Slave Host Value Address*³ CS1 CS2 CS3 CS4 HA0
System control register SYSCR
R/W*¹ —
H'09 H'FFC4 — — — — —
System control register 2 SYSCR2 R/W — H'00 H'FF83 — — — — —
Host interface control
register 1
HICR
R/W — H'F8 H'FFF0 — — — — —
Host interface control
register 2
HICR2
R/W — H'F8 H'FE80 — — — — —
Input data register 1
IDR1
R
W
—
H'FFF4 0
1
1 1 0/1*⁵
Output data register 1 ODR1
R/W R
—
H'FFF5 0 1 1 1 0
Status register 1
STR1
R/(W)*² R
H'00 H'FFF6 0 1 1 1 1
Input data register 2
IDR2
R
W
—
H'FFFC 1
0
1
1
0/1*⁵
Output data register 2 ODR2
R/W R
—
H'FFFD 1 0 1 1 0
Status register 2
Input data register 3
STR2
IDR3
R/(W)*² R
H'00 H'FFFE 1 0 1 1 1
R
W
—
H'FE84 1
1
0
1
0/1^*5
Output data register 3 ODR3
R/W R
—
H'FE85 1 1 0 1 0
Status register 3
Input data register 4
STR3
IDR4
R/(W)*² R
H'00 H'FE86 1 1 0 1 1
R
W
—
H'FE8C 1
1
1
0
0/1^*5
Output data register 4 ODR4
R/W R
—
H'FE8D 1 1 1 0 0
Status register 4
STR4
R/(W)*² R
H'00 H'FE8E 1 1 1 0 1
Module stop control
register
MSTPCRH R/W —
MSTPCRL R/W —
H'3F H'FF86
H'FF H'FF87
—————
—————
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.
556