HD64F2149 Datasheet, PDF (275/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8.11.2 Register Configuration
Table 8.20 summarizes the port A registers.
Table 8.20 Port A Registers
Name
Abbreviation R/W
Port A data direction register PADDR
W
Port A output data register
PAODR
R/W
Port A input data register
PAPIN
R
Notes: 1. Lower 16 bits of the address.
2. PADDR and PAPIN have the same address.
Initial Value
H'00
H'00
Undefined
Address^*1
H'FFAB*²
H'FFAA
H'FFAB*²
Port A Data Direction Register (PADDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A.
Setting a PADDR bit to 1 makes the corresponding port A pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Output Data Register (PAODR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to
PA0). PAODR can always be read or written to, regardless of the contents of PADDR.
PAODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
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