HD64F2149 Datasheet, PDF (353/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
Input capture
signal
ICFA/B/C/D
FRC
N
ICRA/B/C/D
N
Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D)
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last
state in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA
and OCFB.
ø
FRC
N
N+1
OCRA or OCRB
N
Compare-match
signal
OCFA or OCFB
Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB)
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