HD64F2149 Datasheet, PDF (348/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode.
Bit 5
MSTPCRH
0
1
Description
FRT module stop mode is cleared
FRT module stop mode is set
(Initial value)
11.3 Operation
11.3.1 FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
Internal Clock: Any of three internal clocks (ø/2, ø/8, or ø/32) created by division of the system
clock (ø) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR.
Figure 11.3 shows the increment timing.
ø
Internal
clock
FRC input
clock
FRC
N–1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC
increments on the rising edge of the external clock signal.
The pulse width of the external clock signal must be at least 1.5 system clock (ø) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 11.4 shows the increment timing.
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