HD64F2149 Datasheet, PDF (27/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.3.4 Operation in Synchronous Mode.......................................................................... 458
15.3.5 IrDA Operation .................................................................................................... 467
15.4 SCI Interrupts .................................................................................................................... 470
15.5 Usage Notes ....................................................................................................................... 471
Section 16 I²C Bus Interface............................................................................................. 475
16.1 Overview............................................................................................................................ 475
16.1.1 Features ................................................................................................................ 475
16.1.2 Block Diagram...................................................................................................... 476
16.1.3 Input/Output Pins.................................................................................................. 478
16.1.4 Register Configuration ......................................................................................... 479
16.2 Register Descriptions......................................................................................................... 480
16.2.1 I²C Bus Data Register (ICDR).............................................................................. 480
16.2.2 Slave Address Register (SAR) ............................................................................. 483
16.2.3 Second Slave Address Register (SARX).............................................................. 484
16.2.4 I²C Bus Mode Register (ICMR) ........................................................................... 485
16.2.5 I²C Bus Control Register (ICCR) ......................................................................... 488
16.2.6 I²C Bus Status Register (ICSR)............................................................................ 495
16.2.7 Serial/Timer Control Register (STCR) ................................................................ 500
16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 501
16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 503
16.3 Operation ........................................................................................................................... 504
16.3.1 I²C Bus Data Format............................................................................................. 504
16.3.2 Master Transmit Operation .................................................................................. 506
16.3.3 Master Receive Operation .................................................................................... 508
16.3.4 Slave Receive Operation ...................................................................................... 511
16.3.5 Slave Transmit Operation..................................................................................... 513
16.3.6 IRIC Setting Timing and SCL Control ................................................................ 515
16.3.7 Automatic Switching from Formatless Mode to I²C Bus Format........................ 516
16.3.8 Operation Using the DTC .................................................................................... 518
16.3.9 Noise Canceler...................................................................................................... 519
16.3.10 Sample Flowcharts ............................................................................................... 519
16.3.11 Initialization of Internal State............................................................................... 523
16.4 Usage Notes ....................................................................................................................... 525
Section 17 Keyboard Buffer Controller ........................................................................ 531
17.1 Overview............................................................................................................................ 531
17.1.1 Features ................................................................................................................ 531
17.1.2 Block Diagram...................................................................................................... 532
17.1.3 Input/Output Pins.................................................................................................. 533
17.1.4 Register Configuration ......................................................................................... 533
17.2 Register Descriptions......................................................................................................... 534
17.2.1 Keyboard Control Register H (KBCRH) ............................................................. 534
xi