HD64F2149 Datasheet, PDF (604/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18A.4 Interrupts
18A.4.1 IBF1, IBF2, IBF3, IBF4
The host interface can issue four interrupt requests to the slave processor: IBF1, IBF2, IBF3 and
IBF4. They are input buffer full interrupts for input data registers IDR1, IDR2, IDR3 and IDR4
respectively. Each interrupt is enabled when the corresponding enable bit is set.
Table 18A.9 Input Buffer Full Interrupts
Interrupt
IBF1
IBF2
IBF3
IBF4
Description
Requested when IBFIE1 is set to 1 and IDR1 is full
Requested when IBFIE2 is set to 1 and IDR2 is full
Requested when IBFIE3 is set to 1 and IDR3 is full
Requested when IBFIE4 is set to 1 and IDR4 is full
18A.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4
Bits P45DR to P43DR in the port 4 data register (P4DR) and bits PB1ODR and PB0ODR in the
port B data register (PBODR) can be used as host interrupt request latches
The corresponding bits in P4DR are cleared to 0 by the host processor’s read signal (IOR). If CS1
and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared
to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to
0. The corresponding bit in PBODR is cleared to 0 by the host’s read signal (IOR). If CS3 and
HA0 are low, when IOR goes low and the host reads ODR3, HIRQ3 is cleared to 0. If CS4 and
HA0 are low, when IOR goes low and the host reads ODR4, HIRQ4 is cleared to 0. To generate a
host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing
the interrupt, the host’s interrupt handling routine reads the output data register (ODR1, ODR2,
ODR3, or ODR4) and this clears the host interrupt latch to 0.
Table 18A.10 indicates how these bits are set and cleared. Figure 18A.3 shows the processing in
flowchart form.
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