HD64F2149 Datasheet, PDF (910/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

DDCSWR—DDC Switch Register
Bit
7
6
5
SWE
SW
IE
Initial value
0
0
0
Read/Write R/W
R/W
R/W
H'FEE6
4
IF
0
R/(W)*¹
3
CLR3
1
W*²
2
CLR2
1
W*²
1
CLR1
1
W*²
IIC0
0
CLR0
1
W*²
IIC clear bits
Bit 3 Bit 2 Bit 1 Bit 0
CLR3 CLR2 CLR1 CLR0
Description
0 0 — — Setting prohibited
1 0 0 Setting prohibited
1 IIC0 internal latch cleared
1 0 IIC1 internal latch cleared
1 IIC0 and IIC1 internal latches cleared
1 — — — Invalid setting
DDC mode switch interrupt flag
0 No interrupt is requested when automatic format switching
is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
1 An interrupt is requested when automatic format switching
is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
DDC mode switch interrupt enable bit
0 Interrupt when automatic format switching is executed is disabled
1 Interrupt when automatic format switching is executed is enabled
DDC mode switch
0 IIC channel 0 is used with the I²C bus format
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
1 IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
DDC mode switch enable
0 Automatic switching of IIC channel 0 from formatless mode to I²C bus format is disabled
1 Automatic switching of IIC channel 0 from formatless mode to I²C bus format is enabled
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
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