HD64F2149 Datasheet, PDF (573/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.3 Operation
17.3.1 Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on the H8S/2169 or H8S/2149 chip (system) side. KD receives a start bit, 8 data bits (LSB-
first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A
sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.
539