HD64F2149 Datasheet, PDF (359/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Contention between OCR Write and Compare-Match: If a compare-match occurs during the
state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal
is inhibited.
Figure 11.20 shows this type of contention.
If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in
the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of
the automatic addition is not written to OCRA.
Figure 11.21 shows this timing
OCRA or OCRB write cycle
T₁
T₂
ø
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N
M
Write data
Compare-match
signal
Inhibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used)
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