HD64F2149 Datasheet, PDF (628/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

STR1, STR2, STR3 Bit 0—Output Buffer Full (OBF1, OBF2, OBF3A): Set to 1 when the
slave processor writes to ODR. Cleared to 0 when the host processor reads ODR.
Bit 0
OBF
0
1
Description
[Clearing condition]
(Initial value)
When the host processor reads ODR using I/O read cycle, or the slave
processor writes 0 in the OBF bit
[Setting condition]
When the slave processor writes to ODR
STR3 Bit 7—Two-Way Register Input Buffer Full (IBF3B): Set to 1 when the host processor
writes to TWR15. This is an internal interrupt source to the slave processor. IBF3B is cleared to 0
when the slave processor reads TWR15.
Bit 7
IBF3B
0
1
Description
[Clearing condition]
(Initial value)
When the slave processor reads TWR15
[Setting condition]
When the host processor writes to TWR15 using I/O write cycle
STR3 Bit 6—Two-Way Register Output Buffer Full (OBF3B): Set to 1 when the slave
processor writes to TWR15. OBF3B is cleared to 0 when the host processor reads TWR15.
Bit 6
OBF3B
0
1
Description
[Clearing condition]
(Initial value)
When the host processor reads TWR15 using I/O read cycle, or the slave
processor writes 0 in the OBF3B bit
[Setting condition]
When the slave processor writes to TWR15
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