HD64F2149 Datasheet, PDF (488/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format.
Start
1 bit
0 D0 D1
Data
Multi-
proce-
ssor Stop
bit bit
Start
bit
Data
Multi-
proces- Stop
sor bit bit 1
D7 0/1 1 0 D0 D1
D7 0/1
1 ^{Idle state}
(mark state)
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt handling
routine
TXI interrupt
request generated
1 frame
TEI interrupt
request generated
Figure 15.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for
multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
454