HD64F2149 Datasheet, PDF (175/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.3 Overview of Bus Control
6.3.1 Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and wait mode and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with the ABW bit.
Number of Access States: Two or three access states can be selected with the AST bit.
When 2-state access space is designated, wait insertion is disabled. The number of access states on
the burst ROM interface is determined without regard to the AST bit setting.
Wait Mode and Number of Program Wait States: When 3-state access space is designated by
the AST bit, the wait mode and the number of program wait states to be inserted automatically is
selected with WMS1, WMS0, WC1, and WC0. From 0 to 3 program wait states can be selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABW AST WMS1 WMS0 WC1 WC0
0
0
—
—
—
—
1
0
1
—
—
—* —* 0
0
1
1
0
1
1
0
—
—
—
—
1
0
1
—
—
—* —* 0
0
1
1
0
1
Note: * Except when WMS1 = 0 and WMS0 = 1
Bus Specifications (Basic Bus Interface)
Access
Bus Width States
Program
Wait States
16
2
0
16
3
0
3
0
1
2
3
8
2
0
8
3
0
3
0
1
2
3
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