HD64F2149 Datasheet, PDF (715/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU bit in FLMCR2
Wait (y) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
*5
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR2
Wait (β) µs
Disable WDT
End sub
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) µs
Store 128-byte program data in program
data area and reprogram data area
n=1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*4
m=0
Write 128-byte data in RAM reprogram data
area consecutively to flash memory
*1
Sub-routine-call
Write pulse
(z1) µs or (z2) µs
See Note 7 for pulse width
Set PV bit in FLMCR1
Wait (γ) µs
H'FF dummy write to verify address
Increment address
Wait (ε) µs
Read verify data
*2
n←n+1
Note 7: Write Pulse Width
Number of Writes n Write Time (z) µs
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
1...3
z...2
998
z2
999
z2
1000
z2
Note: Use a (z3) µs write pulse for additional
programming.
RAM
Program data storage
area (128 bytes)
Program data =
NG
verify data?
OK
NG
6 ≥ n?
OK
Additional program data computation
Transfer additional program data
to additional program data area
m=1
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
End of 128-byte
NG
data verification?
OK
Clear PV bit in FLMCR1
Wait (η) µs
6 ≥ n?
NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
*1
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 bytes)
Additional write pulse (z3) µs
NG
m = 0?
OK
Clear SWE bit in FLMCR1
n ≥ 1000?
NG
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
Wait (θ) µs
End of programming
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent
verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in
RAM. The reprogram and additional program data contents are modified as programming proceeds.
5. The write pulse of (z1) µs or (z2) µs is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. See section 25, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N.
Program Data Computation Chart
Original Data (D)
Verify Data (V)
0
0
1
1
0
1
Reprogram Data (X)
1
0
1
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Additional Program Data Computation Chart
Reprogram Data (X') Verify Data (V) Additional Program Data (Y)
Comments
0
0
0
Additional programming executed
1
1
Additional programming not executed
1
0
1
1
1
Additional programming not executed
Figure 22.12 Program/Program-Verify Flowchart
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