HD64F2149 Datasheet, PDF (583/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.3.7 Receive Timing
Figure 17.12 shows the receive timing.
ø*
KCLK (pin)
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
N
Internal KD
(KDI)
KBBR7 to
KBBR0
,,,,,,,,,,,,
N+1
N+2
,,,,,,,,,,,,,,,,
Note: * The ø clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active
mode.
Figure 17.12 Receive Counter and KBBR Data Load Timing
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