HD64F2149 Datasheet, PDF (900/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR1—Host Interface Control Register 1
H'FE41
HIF (LPC)
Bit
7
6
5
4
3
2
LPCBSY CLKREQ IRQBSY LRSTB SDWNB PMEB
Initial value
0
0
0
0
0
0
Slave Read/Write R
R
R
R/W R/W R/W
Host Read/Write
—
—
—
—
—
—
1
LSMIB
0
R/W
—
0
LSCIB
0
R/W
—
LSCI output bit
HICR0 HICR1
Bit 0 Bit 0
Description
LSCIE LSCIB
0
0 LSCI output disabled, other function of pin enabled
1 LSCI output disabled, other function of pin enabled
1
0 LSCI output enabled, LSCI pin output goes to 0 level
1 LSCI output enabled, LSCI pin output is high-impedance
LSMI output bit
HICR0 HICR1
Bit 1 Bit 1
LSMIE LSMIB
Description
0
0 LSMI output disabled, other function of pin enabled
1 LSMI output disabled, other function of pin enabled
1
0 LSMI output enabled, LSMI pin output goes to 0 level
1 LSMI output enabled, LSMI pin output is high-impedance
PME output bit
HICR0 HICR1
Bit 2 Bit 2
PMEE PMEB
Description
0
0 PME output disabled, other function of pin enabled
1 PME output disabled, other function of pin enabled
1
0 PME output enabled, PME pin output goes to 0 level
1 PME output enabled, PME pin output is high-impedance
LPC software shutdown bit
0 Normal state
[Clearing conditions] • Writing 0
• LPC hardware reset or LPC software reset
• LPC hardware shutdown
(falling edge of LPCPD signal when SDWNE = 1)
• LPC hardware shutdown release
(rising edge of LPCPD signal when SDWNE = 0)
1 LPC software shutdown state
[Setting condition] • Writing 1 after reading SDWNB = 0
LPC software reset bit
0 Normal state
[Clearing conditions] • Writing 0
• LPC hardware reset
1 LPC software reset state
[Setting condition] • Writing 1 after reading LRSTB = 0
SERIRQ busy
LCLK request
0 SERIRQ transfer frame wait state
[Clearing conditions] • LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• End of SERIRQ transfer frame
1 SERIRQ transfer processing in progress
[Setting condition] • Start of SERIRQ transfer frame
0 No LCLK restart request
[Clearing conditions] • LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• SERIRQ is set to continuous mode
• There are no further interrupts for transfer to the host in quiet mode
LPC busy
1 LCLK restart request issued
[Setting condition] • In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped
0 Host interface is in transfer cycle wait state
• Bus idle, or transfer cycle not subject to processing is in progress
• Cycle type or address indeterminate during transfer cycle
[Clearing conditions] • LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• Forced termination (abort) of transfer cycle subject to processing
• Normal termination of transfer cycle subject to processing
1 Host interface is performing transfer cycle processing
[Setting condition] • Match of cycle type and address
866