HD64F2149 Datasheet, PDF (537/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
Bit 3
CLR3
0
1
Bit 2
CLR2
0
1
—
Bit 1
CLR1
—
0
1
—
Bit 0
CLR0
—
0
1
0
1
—
Description
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
16.2.9 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at
the end of the bus cycle, and a transition is made to module stop mode. For details, see section
24.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
503