HD64F2149 Datasheet, PDF (30/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

20.1.4 Register Configuration ......................................................................................... 632
20.2 Register Descriptions......................................................................................................... 632
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 632
20.2.2 A/D Control/Status Register (ADCSR)................................................................ 633
20.2.3 A/D Control Register (ADCR)............................................................................. 636
20.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 637
20.2.5 Module Stop Control Register (MSTPCR) .......................................................... 638
20.3 Interface to Bus Master...................................................................................................... 639
20.4 Operation ........................................................................................................................... 640
20.4.1 Single Mode (SCAN = 0) ..................................................................................... 640
20.4.2 Scan Mode (SCAN = 1) ....................................................................................... 642
20.4.3 Input Sampling and A/D Conversion Time.......................................................... 644
20.4.4 External Trigger Input Timing ............................................................................. 645
20.5 Interrupts............................................................................................................................ 645
20.6 Usage Notes ....................................................................................................................... 646
Section 21 RAM ................................................................................................................... 653
21.1 Overview............................................................................................................................ 653
21.1.1 Block Diagram...................................................................................................... 653
21.1.2 Register Configuration ......................................................................................... 654
21.2 System Control Register (SYSCR).................................................................................... 654
21.3 Operation ........................................................................................................................... 655
21.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1))................................................ 655
21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 655
Section 22 ROM ................................................................................................................... 657
22.1 Overview............................................................................................................................ 657
22.1.1 Block Diagram...................................................................................................... 657
22.1.2 Register Configuration.......................................................................................... 658
22.2 Register Descriptions......................................................................................................... 658
22.2.1 Mode Control Register (MDCR).......................................................................... 658
22.3 Operation ........................................................................................................................... 659
22.4 Overview of Flash Memory............................................................................................... 660
22.4.1 Features ................................................................................................................ 660
22.4.2 Block Diagram...................................................................................................... 661
22.4.3 Flash Memory Operating Modes.......................................................................... 662
22.4.4 Pin Configuration ................................................................................................. 666
22.4.5 Register Configuration ......................................................................................... 666
22.5 Register Descriptions......................................................................................................... 667
22.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 667
22.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 669
22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 670
22.5.4 Serial/Timer Control Register (STCR) ................................................................ 671
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