HD64F2149 Datasheet, PDF (480/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Initialization
Start reception
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
FER flags in SSR
[2]
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
PER∨FER∨ORER= 1?
Yes
[3]
performing the appropriate error
handling, ensure that the ORER,
PER, and FER flags are all
No
Error handling
cleared to 0. Reception cannot
be resumed if any of these flags
(Continued on next page) ^{are set to 1. In the case of a}
framing error, a break can be
Read RDRF flag in SSR
[4]
detected by reading the value of
the input port corresponding to
the RxD pin.
No
RDRF= 1?
[4] SCI status check and receive
data read :
Yes
Read SSR and check that RDRF
= 1, then read the receive data in
Read receive data in RDR, and
clear RDRF flag in SSR to 0
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
Figure 15.7 Sample Serial Reception Data Flowchart
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