HD64F2149 Datasheet, PDF (102/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 2.16 shows the stack after exception handling ends.
Normal mode
Advanced mode
SP
CCR
CCR*
PC
(16 bits)
SP
CCR
PC
(24 bits)
Note: * Ignored when returning.
Figure 2.16 Stack Structure after Exception Handling (Examples)
2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, all CPU internal operations are halted.
There is one other bus master in addition to the CPU: the data transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also
three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In
medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module
stop mode permits halting of the operation of individual modules, other than the CPU. Subactive
mode, subsleep mode, and watch mode are power-down modes that use subclock input. For
details, refer to section 24, Power-Down State.
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