HD64F2149 Datasheet, PDF (720/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Normal operation mode
Program mode
Erase mode
RD VF PR ER FLER = 0
RES = 0 or STBY = 0
Reset or hardware standby
(hardware protection)
RD VF PR ER FLER = 0
Error
occurrence*1
Error occurrence^*2
RES = 0 or
STBY = 0
RES = 0 or
STBY = 0
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
Error protection mode
RD VF^*4 PR ER FLER = 1
Software standby,
sleep, subsleep, and
watch mode
Software standby,
sleep, subsleep, and
watch mode release
Error protection
mode (software standby,
sleep, subsleep, and watch )
RD VF PR ER FLER = 1
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state^*3
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
executed for a transition to subactive mode
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4. VF in subactive mode
Figure 22.14 Flash Memory State Transitions
22.9 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or erased
(when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*¹,
to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*², possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
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