HD64F2149 Datasheet, PDF (11/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

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Revision (See Manual for Details)
16.3.10 Sample Flowcharts Figure 16.14 Flowchart for Master Transmit Mode
Completely amended
Figure 16.15 Flowchart for Master Receive Mode
Completely amended
16.3.11 Initialization of
Internal State
Notes on Initialization: Description amended
16.4 Usage Notes
Table 16.7 Permissible SCL Rise Time Values
φ = 16 MHz or more deleted
Table16.8 I²C Bus Timing
φ = 16 MHz or more deleted
Notes on start condition Issuance for Retransmission
Notes on I²C Bus Interface Stop Condition Instruction
Issuance added
17.2.4 Module Stop Control Added
Register
18A.2.1 System Control
Register
Bit 1: Description amended
18A.5 Usage Note
(2) Data contention on the host interface data bus (HDB)
added
18B.2.3 Host Interface
HICR2 bits 3 to 0: Description amended when IBFIE3 is
Control Registers 2 and 3 set to 1
18B.2.4 LPC Channel 3
Address Register
LADR3L bit 2: Description amended
18B.2.9 SERIRQ Control Names of SERIRQ interrupt sources amended
Registers
18B.3.4 Host Interface
Shutdown Function
Table 18B.5 Scope of HIF Pin Shutdown
CLKRUN I/O amended
Note added
18B.4.1 IBF1, IBF2, IBF3, Table 18B.7 Receive Complete Interrupts are Error
ERRI
interrupt
IBF3 description amended
18B.5 Usage Note
(3) added
20.1.1 Features
Conversion time amended
20.2.3 A/D Control Register Bits 5 to 0: Description amended
20.6 Usage Notes
Table 20.5 Analog Pin Ratings
Permissible signal source impedance max. value
amended
Note added