HD64F2149 Datasheet, PDF (411/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using
TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold.
Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is
shown in figure 13.2.
Table 13.3 Examples of TCR Settings
Bit(s)
7
6
5
4 and 3
Abbreviation
CMIEB
CMIEA
OVIE
CCLR1, CCLR0
2 to 0
CKS2 to CKS0
Contents
0
0
0
11
001
Description
Interrupts due to compare-match and overflow
are disabled
TCNT is cleared by the rising edge of the
external reset signal (IHI signal)
Incremented on internal clock: ø
Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings
H'07
H'0F
H'1F
H'3F
H'7F
ø:10 MHz
0.8 µs
1.6 µs
3.2 µs
6.4 µs
12.8 µs
IHI signal
PDC signal
IHI signal is tested
at compare-match
TCNT
TCORB
(threshold)
Counter reset
caused by
IHI signal
Counter clear At the 2nd compare-match,
caused by
IHI signal is not tested
TCNT overflow
Figure 13.2 Timing Chart for PWM Decoding
377