HD64F2149 Datasheet, PDF (648/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Frame
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16
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18
Serial Interrupt Transfer Cycle
Contents
Drive
Source
Number
of States
Start
Slave
6
Host
HIRQ0
Slave
3
HIRQ1
Slave
3
SMI
Slave
3
HIRQ3
Slave
3
HIRQ4
Slave
3
HIRQ5
Slave
3
HIRQ6
Slave
3
HIRQ7
Slave
3
HIRQ8
Slave
3
HIRQ9
Slave
3
HIRQ10
Slave
3
HIRQ11
Slave
3
HIRQ12
Slave
3
HIRQ13
Slave
3
HIRQ14
Slave
3
HIRQ15
Slave
3
IOCHCK
Slave
3
Stop
Host
Undefined
Notes
In quiet mode only, slave drive possible in first
state, then next 3 states 0-driven by host
Drive possible in LPC channel 1
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channels 2 and 3
Drive possible in LPC channel 1
First, 1 or more idle states, then 2 or 3 states
0-driven by host
2 states: Quiet mode next
3 states: Continuous mode next
There are two modes—continuous mode and quiet mode—for serialized interrupts. The mode
initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer
cycle that ended before that cycle.
In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet
mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt
transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate
interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-
down state. In order for a slave to transfer an interrupt request in this case, a request to restart the
clock must first be issued to the host. For details see section 18B.3.6, Host Interface Clock Start
Request (CLKRUN).
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