HD64F2149 Datasheet, PDF (192/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.6 Idle Cycle
6.6.1 Operation
When the H8S/2169 or H8S/2149 chip accesses external space, it can insert a 1-state idle cycle
(T_I) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle
cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal
mode.
Figure 6.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
ø
Address bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
ø
Address bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
RD
HWR, LWR
Data bus
RD
HWR, LWR
Data bus
Long output ^{Data collision}
floating time
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.15 Example of Idle Cycle Operation
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