HD64F2149 Datasheet, PDF (627/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 15 to 4
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
1
0
1
Bit 1
0
1
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
STR1 read
STR2 read
STR1, STR2 Bits 7 to 4 and 2—Defined by User (DBU17 to DBU14, DBU12; DBU27 to
DBU24, DBU22)
STR3 Bit 2— Defined by User (DBU32)
The user can use these bits as necessary.
STR1, STR2, STR3 Bit 3—Command/Data (C/D1, C/D2, C/D3): When the host processor
writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR
contains data or a command.
Bit 3
C/D
0
1
Description
Contents of data register (IDR) are data
Contents of data register (IDR) are a command
(Initial value)
STR1, STR2, STR3 Bit 1—Input Buffer Full (IBF1, IBF2, IBF3A): Set to 1 when the host
processor writes to IDR. This bit is an internal interrupt source to the slave processor. IBF is
cleared to 0 when the slave processor reads IDR.
The IBF1 flag setting and clearing conditions are diffrent when the fast A20 gate is used. For
details see table 18B.4, Fast A20 gate Output Signals.
Bit 1
IBF
0
1
Description
[Clearing condition]
When the slave processor reads IDR
[Setting condition]
When the host processor writes to IDR using I/O write cycle
(Initial value)
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