HD64F2149 Datasheet, PDF (535/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the access of CPU to the
flash memory control registers, the power-down mode control registers, and the supporting
module control registers. See section 3.2.4, Serial/Timer Control Register (STCR).
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).
16.2.8 DDC Switch Register (DDCSWR)
Bit
Initial value
Read/Write
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)^*1
3
CLR3
1
W^*2
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
2
CLR2
1
W^*2
1
CLR1
1
W^*2
0
CLR0
1
W^*2
DDCSWR is an 8-bit readable/writable register that controls the IIC channel 0 automatic format
switching function and IIC internal latch clearance.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC
channel 0 from formatless mode to the I²C bus format.
Bit 7
SWE
0
1
Description
Automatic switching of IIC channel 0 from formatless mode to I²C bus
format is disabled
Automatic switching of IIC channel 0 from formatless mode to I²C bus
format is enabled
(Initial value)
Bit 6—DDC Mode Switch (SW): Selects either formatless mode or the I²C bus format for IIC
channel 0.
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