HD64F2149 Datasheet, PDF (428/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.1.4 Register Configuration
The WDT has four registers, as summarized in table 14.2. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 14.2 WDT Registers
Address*¹
Channel Name
Abbreviation R/W
Initial Value Write*² Read
0
Timer control/status TCSR0
R/(W)*³ H'00
H'FFA8 H'FFA8
register 0
Timer counter 0
TCNT0
R/W
H'00
H'FFA8 H'FFA9
1
Timer control/status TCSR1
R/(W)*³ H'00
H'FFEA H'FFEA
register 1
Timer counter 1
TCNT1
R/W
H'00
H'FFEA H'FFEB
Common System control
register
SYSCR
R/W
H'09
H'FFC4 H'FFC4
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 14.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
14.2 Register Descriptions
14.2.1 Timer Counter (TCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (RESO) output,
an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, depending
on the mode selected by the WT/IT bit and RST/NMI bit.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
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