HD64F2149 Datasheet, PDF (35/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 1 Overview
1.1 Overview
The H8S/2149 and H8S/2169 F-ZTAT™ is a microcomputer (MCU) built around the H8S/2000
CPU, employing Hitachi’s proprietary architecture, and equipped with on-chip supporting
functions required for system configuration.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting functions required for system configuration include a data transfer controller
(DTC) bus master, ROM and RAM memory, a 16-bit free-running timer module (FRT), an 8-bit
timer module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX),
serial communication interface (SCI), PS/2-compatible keyboard buffer controller, I²C bus
interface (IIC), host interfaces (HIF:LPC and HIF:XBS), D/A converter (DAC), A/D converter
(ADC), and I/O ports. The H8S/2169 F-ZTAT™ has all of the same I/O ports as the H8S/2149 F-
ZTAT™, plus 40 additional I/O ports.
The on-chip ROM is 64-kbyte flash memory (F-ZTAT™*). The ROM is connected to the CPU by
a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction
fetching has been speeded up, and processing speed increased.
Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and
single-chip mode or externally expanded modes.
The features of the H8S/2149 and H8S/2169 F-ZTAT™ are shown in table 1.1.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
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