HD64F2149 Datasheet, PDF (647/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

LCLK
SERIRQ
Drive source
SL
or
Start frame
IRQ0 frame IRQ1 frame IRQ2 frame
H
H
RT SRT SRT SRT
START
IRQ1 Host controller
None
IRQ1
None
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
LCLK
SERIRQ
Driver
IRQ14 frame IRQ15 frame IOCHCK frame
SRT SRT SRT I
Stop frame
H
RT
Next cycle
None
IRQ15
None
STOP
Host controller
START
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 18B.6 SERIRQ Timing
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
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