HD64F2149 Datasheet, PDF (523/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 7—I²C Bus Interface Enable (ICE): Selects whether or not the I²C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I²C bus interface module is disabled and the
internal state is cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE
0
1
Description
I²C bus interface module disabled, with SCL and SDA signal pins
set to port function
(Initial value)
I²C bus interface module internal state initialized
SAR and SARX can be accessed
I²C bus interface module enabled for transfer operations (pins SCL and SCA are driving
the bus)
ICMR and ICDR can be accessed
Bit 6—I²C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I²C
bus interface to the CPU.
Bit 6
IEIC
0
1
Description
Interrupts disabled
Interrupts enabled
(Initial value)
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I²C bus interface operates in master mode or slave mode.
TRS selects whether the I²C bus interface operates in transmit mode or receive mode.
In master mode with the I²C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
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