HD64F2149 Datasheet, PDF (617/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR1 Bit 5—SERIRQ Busy (IRQBSY): Indicates that the host interface’s SERIRQ signal is
engaged in transfer processing.
HICR1
Bit 5
IRQBSY
0
1
Description
SERIRQ transfer frame wait state
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• End of SERIRQ transfer frame
SERIRQ transfer processing in progress
[Setting condition]
• Start of SERIRQ transfer frame
(Initial value)
HICR1 Bit 4—LPC Software Reset Bit (LRSTB): Resets the host interface. For the scope of
initialization by an LPC reset, see section 18B.3.4, Host Interface Shutdown Function.
HICR1
Bit 4
LRSTB
0
1
Description
Normal state
[Clearing conditions]
• Writing 0
• LPC hardware reset
LPC software reset state
[Setting condition]
• Writing 1 after reading LRSTB = 0
(Initial value)
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