HD64F2149 Datasheet, PDF (467/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.2.9 Serial Interface Mode Register (SCMR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
SDIR SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W R/W
—
R/W
SCMR is an 8-bit readable/writable register used to select SCI functions.
SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3
SDIR
0
1
Description
TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
(Initial value)
Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in
SMR.
Bit 2
SINV
0
1
Description
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
(Initial value)
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be
written in this bit.
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