HD64F2149 Datasheet, PDF (351/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
Input capture
input pin
Input capture
signal
ICRA/B/C/D read cycle
T₁
T₂
Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D is Read)
Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and
ICRB.
Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
ø
FTIA
Input capture
signal
FRC
n
n+1
N
N+1
ICRA
M
n
nN
ICRC
mM
Mn
Figure 11.9 Buffered Input Capture Timing (Usual Case)
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