HD64F2149 Datasheet, PDF (578/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.3.3 Receive Abort
The H8S/2169 or H8S/2149 device (system side) can forcibly abort transmission from the device
connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds
the clock low. During reception, the keyboard also outputs a clock for synchronization, and the
clock is monitored when the keyboard output clock is high. If the clock is low at this time, the
keyboard judges that there is an abort request from the system, and data transmission from the
keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain
period. A sample receive abort processing flowchart is shown in figure 17.7, and the receive abort
timing in figure 17.8.
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