HD64F2149 Datasheet, PDF (407/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

13.2.4 Edge Sense Register (SEDGR)
Bit
7
6
5
4
3
2
1
0
VEDG HEDG CEDG HFEDG VFEDG PREQF IHI
IVI
Initial value
0
0
0
0
0
0
—^*2
—^*2
Read/Write R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1 R/(W)^*1
R
R
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin.
Bit 7
VEDG
0
1
Description
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
(Initial value)
Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
Bit 6
HEDG
0
1
Description
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
(Initial value)
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