HD64F2149 Datasheet, PDF (975/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TISR—Timer Input Select Register
Bit
7
6
5
—
—
—
Initial value
1
1
1
Read/Write
—
—
—
H'FFF5
4
3
2
—
—
—
1
1
1
—
—
—
TMRY
1
0
—
IS
1
0
—
R/W
Input select
0 IVG signal is selected
1 VSYNCI/TMIY (TMCIY/TMRIY) is selected
STR1—Status Register 1
STR2—Status Register 2
Bit
Initial value
Slave R/W
Host R/W
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
H'FFF6
H'FFFE
3
2
C/D DBU
0
0
R
R/W
R
R
HIF (XBS)
HIF (XBS)
1
0
IBF OBF
0
0
R R/(W)*
R
R
User-defined bits
Output buffer full
0 [Clearing condition]
When the host processor reads ODR
or the slave writes 0 in the OBF bit
1 [Setting condition]
When the slave processor writes to
ODR
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command
Note: * Only 0 can be written, to clear the flag.
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