HD64F2149 Datasheet, PDF (1024/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

C.11 Port B Block Diagram
Hardware
standby
*¹
PBn
*²
Mode 2, 3
EXPE
Reset
R
Q
D
External
address write
PBnDDR
C
EXPE
WPBD
ABW
(D0, D1)
Reset
RPBO
R
QD
PBnODR
C
WPB
External address
read _{(D0, D1)}
HIF : XBS
RESOBF3, 4
(Reset HIRQ3,
HIRQ4)
HIF : LPC
LSMI, LSCI output
Output enable
RPB
LSMI, LSCI input
WPBD : Write to PBDDR
WPB : Write to PBODR
RPBO : Read PBODR
RPB : Read port B
n = 0, 1
Notes: 1. Output enable signal
2. Open drain control signal
Wakeup event interrupt
input
WUEMRn
Figure C.40 Port B Block Diagram (Pins PB0 and PB1)
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