HD64F2149 Datasheet, PDF (625/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.2.7 Two-Way Data Registers (TWR0 to TWR15)
• TWR0MW
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R
W
6
Bit 6
—
R
W
5
Bit 5
—
R
W
4
Bit 4
—
R
W
3
Bit 3
—
R
W
2
Bit 2
—
R
W
1
Bit 1
—
R
W
0
Bit 0
—
R
W
• TWR0SW
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
W
R
6
Bit 6
—
W
R
5
Bit 5
—
W
R
4
Bit 4
—
W
R
3
Bit 3
—
W
R
2
Bit 2
—
W
R
1
Bit 1
—
W
R
0
Bit 0
—
W
R
• TWR1 to TWR15
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R/W
R/W
6
Bit 6
—
R/W
R/W
5
Bit 5
—
R/W
R/W
4
Bit 4
—
R/W
R/W
3
Bit 3
—
R/W
R/W
2
Bit 2
—
R/W
R/W
1
Bit 1
—
R/W
R/W
0
Bit 0
—
R/W
R/W
TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor and the
host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the
same address for both the host address and the slave address. TWR0MW is a write-only register to
the host processor, and a read-only register to the slave processor, while TWR0SW is a write-only
register to the slave processor and a read-only register to the host processor. When the host and
slave processors begin a write, after the respective TWR0 registers have been written to, access
right arbitration for simultaneous access is performed by checking the status flags to see if those
writes were valid. For the registers selected from the host according to the I/O address, see section
18B.2.4, LPC Channel 3 Address Register (LADR3).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host.
The initial values of TWR0 to TWR15 after a reset and in standby mode are undetermined.
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