HD64F2149 Datasheet, PDF (602/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 18A.7 Fast A20 Gate Output Signal
HA0 Data/Command
Internal CPU
Interrupt Flag
1
H'D1 command
0
0
1 data*¹
0
1
H'FF command
0
1
H'D1 command
0
0
0 data*²
0
1
H'FF command
0
1
H'D1 command
0
0
1 data*¹
0
1/0 Command other than H'FF
1
and H'D1
1
H'D1 command
0
0
0 data*²
0
1/0 Command other than H'FF
1
and H'D1
1
H'D1 command
0
1
Command other than H'D1
1
1
H'D1 command
0
1
H'D1 command
0
1
H'D1 command
0
0
Any data
0
1
H'D1 command
0
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
GA20
(P81)
Q
1
Q (1)
Q
0
Q (0)
Q
1
Q (1)
Q
0
Q (0)
Q
Q
Q
Q
Q
1/0
Q(1/0)
Remarks
Turn-on sequence
Turn-off sequence
Turn-on sequence
(abbreviated form)
Turn-off sequence
(abbreviated form)
Cancelled sequence
Retriggered sequence
Consecutively executed
sequences
18A.3.4 Host Interface Pin Shutdown Function
Host interface output can be placed in the high-impedance state according to the state of the
HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register when the HI12E bit is set to 1 enables
the HIFSD pin. The HIF constantly monitors the HIFSD pin, and when this pin goes low, places
the host interface output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the
high-impedance state. At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3,
CS4, IOW, IOR, and HA0) are disabled (fixed at the high input state internally) regardless of the
pin states, and the signals of the multiplexed functions of these pins (input block) are similarly
fixed internally. As a result, the host interface I/O pins (HDB7 to HDB0) also go to the high-
impedance state.
This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the high-
level state, the pins are restored to their normal operation as host interface pins.
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