HD64F2149 Datasheet, PDF (60/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Pin No.
Type
FP-100B,
Symbol TFP-100B TFP-144 I/O
Name and Function
Keyboard PS2AC 31
buffer PS2BC 21
controller PS2CC 11
(PS2) _{PS2AD 30}
PS2BD 20
PS2CD 10
39
Input/ PS2 clock: Keyboard buffer controller
37
Ouput synchronization clock input/output pins.
34
38
Input/ PS2 data: Keyboard buffer controller data
35
Ouput input/output pins.
33
Host
HDB7 to
interface HDB0
(HIF:XBS) _{CS1, CS2}
ECS2,
CS3, CS4
89–82
18, 94,
25, 81, 80
128-121 Input/
Ouput
19, 130, Input
24, 118,
117
Host interface data bus: Bidirectional 8-bit
bus for accessing the host interface (XBS).
Chip select 1, 2, 3, 4: Input pins for
selecting host interface (XBS) channel 1 to
4.
IOR
22
21
Input I/O read: Input pin that enables reading
from the host interface (XBS).
IOW
19
20
Input I/O write: Input pin that enables writing to
the host interface (XBS).
HA0
93
129
Input Command/data: Input pin that indicates
whether an access is a data access or
command access.
GA20
94
130
Output GATE A20: A20 gate control signal output
pin.
HIRQ11 52
HIRQ1 53
HIRQ12 54
HIRQ3 91
HIRQ4 90
2
Output Host interrupt 11, 1, 12, 3, 4: Output pins
3
for interrupt requests to the host.
4
120
119
HIFSD 95
131
Input Host interface shutdown: Control input
pin used to place host interface (XBS)
input/output pins in the high-impedance /
cutoff state.
Host
LAD3 to
interface LAD0
(HIF:LPC) _LFRAME
85–82
86
124-121 Input/
Ouput
125
Input
Address/data: LPC command, address,
and data input/output pins.
LPC frame: Input pin that indicates the
start of an LPC cycle or forced termination
of an abnormal LPC cycle.
LRESET 87
126
Input LPC reset: Input pin that indicates an LPC
reset.
LCLK
88
127
Input LPC clock: The LPC clock input pin.
26